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CoolRunner-II CPLD Family
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Product Specification Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts - SSTL2_1,SSTL3_1, and HSTL_1 on 128 macrocell and denser devices - Hot pluggable PLA architecture - Superior pinout retention - 100% product term routability across function block Wide package availability including fine pitch: - Chip Scale Package (CSP) BGA, Fine Line BGA, TQFP, PQFP, VQFP, PLCC, and QFN packages - Pb-free available for all packages Design entry/verification using Xilinx and industry standard CAE tools Free software support for all densities using Xilinx WebPACKTM Industry leading nonvolatile 0.18 micron CMOS process - Guaranteed 1,000 program/erase cycles - Guaranteed 20 year data retention -
Features
* Optimized for 1.8V systems - Industry's fastest low power CPLD - Densities from 32 to 512 macrocells Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation -- 1.5V to 3.3V Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - On-The-Fly Reconfiguration (OTF) - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt trigger input (per pin) - Multiple I/O banks on all devices - Unsurpassed low power management * DataGATE external signal control - Flexible clocking modes * Optional DualEDGE triggered registers * Clock divider (/ 2,4,6,8,10,12,14,16) * CoolCLOCK - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Abundant product term clocks, output enables and set/resets - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on select I/O pins - Optional configurable grounds on unused I/Os
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Family Overview
Xilinx CoolRunnerTM-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3TM family in a single CPLD. This means that the exact same parts can be used for high-speed data communications/ computing systems and leading edge portable products, with the added benefit of In System Programming. Low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. Clocking techniques and other power saving features extend the users' power budget. The design features are supported starting with Xilinx ISE 4.1i ISE WebPACK. Additional details can be found in Further Reading, page 13. Table 1 shows the macrocell capacity and key timing parameters for the CoolRunner-II CPLD family.
Table 1: CoolRunner-II CPLD Family Parameters XC2C32A Macrocells Max I/O TPD (ns) TSU (ns) TCO (ns) FSYSTEM1 (MHz) 32 33 3.8 1.9 3.7 323 XC2C64A 64 64 4.6 2.0 3.9 263 XC2C128 128 100 5.7 2.4 4.2 244 XC2C256 256 184 5.7 2.4 4.5 256 XC2C384 384 240 7.1 2.9 5.8 217 XC2C512 512 270 7.1 2.6 5.8 179
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CoolRunner-II CPLD Family Table 2: CoolRunner-II CPLD DC Characteristics XC2C32A ICC (A), 0 MHz, 25C (typical) ICC (mA), 50 MHz, 70C (max)
ICC is dynamic current.
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XC2C64A 17 5
XC2C128 19 10
XC2C256 21 27
XC2C384 23 45
XC2C512 25 55
16 2.5
Table 2 shows key DC characteristics for the CoolRunner-II family. Table 3 shows the CoolRunner-II CPLD package offering with corresponding I/O count. All packages are surface mount, with over half of them being ball-grid technologies. The ultra tiny packages permit maximum functional capacity in the smallest possible area. The CMOS technology used in CoolRunner-II CPLDs generates minimal heat, allowing the use of tiny packages during high-speed operation.
With the exception of the new Pb-free QF packages, there are at least two densities present in each package with three in the VQ100 (100-pin 1.0mm QFP) and TQ144 (144-pin 1.4mm QFP), and in the FT256 (256-ball 1.0mm spacing FLBGA). The FT256 is particularly important for slim dimensioned portable products with mid- to high-density logic requirements.
Table 3: CoolRunner-II CPLD Family Packages and I/O Count XC2C32 QFG32(1) PC44 PCG44(1) VQ44 VQG44(1) QFG48(1) CP56 CPG56(1) VQ100 VQG100(1) CP132 CPG132(1) TQ144 TQG144(1) PQ208 PQG208(1) FT256 FTG256(1) FG324 FGG324(1) 33 33 33 XC2C32A 21 33 33 33 33 33 33 64 45 33 XC2C64 33 XC2C64A 33 33 33 33 37 45 45 64 64 XC2C128 80 80 100 100 100 100 XC2C256 80 80 106 106 118 118 173 173 184 184 XC2C384 118 118 173 173 212 212 240 240 XC2C512 173 173 212 212 270 270
Notes: 1. The letter "G" as the third character indicates a Pb-free package.
Table 4 details the distribution of advanced features across the CoolRunner-II CPLD family. The family has uniform basic features with advanced features included in densities where they are most useful. For example, it is very unlikely that four I/O banks are needed on 32 and 64 macrocell
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parts, but very likely they are for 384 and 512 macrocell parts. The I/O banks are groupings of I/O pins using any one of a subset of compatible voltage standards that share the same VCCIO level. (See Table 5 for a summary of CoolRunner-II I/O standards.)
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CoolRunner-II CPLD Family
Table 4: CoolRunner-II CPLD Family Features XC2C32 IEEE 1532 I/O banks Clock division DualEDGE Registers DataGATE LVTTL LVCMOS33, 25, 18, and 15(1) SSTL2_1 SSTL3_1 HSTL_1 Configurable ground Quadruple data security Open drain outputs Hot plugging Schmitt Inputs 1 XC2C32A 2 XC2C64 1 XC2C64A 2 XC2C128 2 XC2C256 2 XC2C384 4 XC2C512 4
(1) LVCMOS15 requires the use of Schmitt-trigger inputs.
Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low power CPLDs. The underlying architecture is a traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Function Blocks use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared among any of the macrocells of the FB. Design software can efficiently synthesize and optimize logic that is subsequently fit to the FBs and connected with the ability to utilize a very high percentage of device resources. Design changes are easily and automatically managed by the software, which exploits the 100% routability of the Programmable Logic Array within each FB. This extremely robust
building block delivers the industry's highest pinout retention, under very broad design conditions. The architecture will be explained by expanding the detail as we discuss the underlying Function Blocks, logic and interconnect. The design software automatically manages these device resources so that users can express their designs using completely generic constructs without knowledge of these architectural details. More advanced users can take advantage of these details to more thoroughly understand the software's choices and direct its results. Figure 1 shows the high-level architecture whereby Function Blocks attach to pins and interconnect to each other within the internal interconnect matrix. Each FB contains 16 macrocells. The BSC path is the JTAG Boundary Scan Con-
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CoolRunner-II CPLD Family trol path. The BSC and ISP block has the JTAG controller and In-System Programming Circuits.
BSC Path Clock and Control Signals
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Function Block 1
I/O Pin I/O Pin
Function Block n
MC1 MC2
16 FB 16 FB I/O Pin I/O Pin
MC1 MC2
I/O Blocks
16
PLA
40
AIM
PLA
40
16
I/O Pin 16
MC16
Direct Inputs
MC16
Direct Inputs 16
I/O Blocks
I/O Pin
JTAG
BSC and ISP
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Figure 1: CoolRunner-II CPLD Architecture
Function Block
The CoolRunner-II CPLD Function Blocks contain 16 macrocells, with 40 entry sites for signals to arrive for logic creation and connection. The internal logic engine is a 56 product term PLA. All Function Blocks, regardless of the number contained in the device, are identical. For a high-level view of the Function Block, see Figure 2.
MC1 MC2
is extremely flexible, and very robust when compared to fixed or cascaded product term function blocks. Classic CPLDs typically have a few product terms available for a high-speed path to a given macrocell. They rely on capturing unused p-terms from neighboring macrocells to expand their product term tally, when needed. The result of this architecture is a variable timing model and the possibility of stranding unusable logic within the FB. The PLA is different -- and better. First, any product term can be attached to any OR gate inside the FB macrocell(s). Second, any logic function can have as many p-terms as needed attached to it within the FB, to an upper limit of 56. Third, product terms can be re-used at multiple macrocell OR functions so that within a FB, a particular logical product need only be created once, but can be re-used up to 16 times within the FB. Naturally, this plays well with the fitting software, which identifies product terms that can be shared. The software places as many of those functions as it can into FBs, so it happens for free. There is no need to force macrocell functions to be adjacent or any other restriction save residing in the same FB, which is handled by the software. Functions need not share a common clock, common set/reset or common output enable to take full advantage of the PLA. Also, every product term arrives with the same time delay incurred. There are no cascade time adders for putting more product terms in the FB. When the FB product term budget is reached, there is a small interconnect timing penalty to route signals to another FB to continue creating logic. Xilinx design software handles all this automatically.
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PLA
16
Out To AIM
MC16
3
Global Set/Reset
Global Clocks
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Figure 2: CoolRunner-II CPLD Function Block At the high level, it is seen that the product terms (p-terms) reside in a programmable logic array (PLA). This structure
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CoolRunner-II CPLD Family resets, and output enables. Each macrocell flip-flop is configurable for either single edge or DualEDGE clocking, providing either double data rate capability or the ability to distribute a slower clock (thereby saving power). For single edge clocking or latching, either clock polarity may be selected per macrocell. CoolRunner-II macrocell details are shown in Figure 3. Note that in Figure 4, standard logic symbols are used except the trapezoidal multiplexers have input selection from statically programmed configuration select lines (not shown). Xilinx application note XAPP376 gives a detailed explanation of how logic is created in the CoolRunner-II CPLD family.
Macrocell
The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. Users can develop sum of product (SOP) logic expressions that comprise up to 40 inputs and span 56 product terms within a single function block. The macrocell can further combine the SOP expression into an XOR gate with another single p-term expression. The resulting logic expression's polarity is also selectable. As well, the logic function can be pure combinatorial or registered, with the storage element operating selectably as a D or T flip-flop, or transparent latch. Available at each macrocell are independent selections of global, function block level or local p-term derived clocks, sets,
From AIM
40
49 P-terms To PTA, PTB, PTC of other macrocells 4 P-terms CTC, CTR, CTS, CTE PTA Direct Input from I/O Block Feedback to AIM
PTB
VCC
PTC
PTA CTS GSR GND
GND
D/T PLA OR Term
S Q FIF Latch DualEDGE R
To I/O Block
PTC
CE CK
CTC PTC
GCK0 GCK1 GCK2 PTA CTR GSR GND
DS090_03_121201
Figure 3: CoolRunner-II CPLD Macrocell When configured as a D-type flip-flop, each macrocell has an optional clock enable signal permitting state hold while a clock runs freely. Note that Control Terms (CT) are available to be shared for key functions within the FB, and are generally used whenever the exact same logic function would be repeatedly created at multiple macrocells. The CT product terms are available for FB clocking (CTC), FB asynchronous set (CTS), FB asynchronous reset (CTR), and FB output enable (CTE). Any macrocell flip-flop can be configured as an input register or latch, which takes in the signal from the macrocell's I/O pin, and directly drives the AIM. The macrocell combinational functionality is retained for use as a buried logic node if needed. FToggle is the maximum clock frequency to which a T flip-flop can reliably toggle.
Advanced Interconnect Matrix (AIM)
The Advanced Interconnect Matrix is a highly connected low power rapid switch. The AIM is directed by the software to deliver up to a set of 40 signals to each FB for the creation of logic. Results from all FB macrocells, as well as, all pin inputs circulate back through the AIM for additional connection available to all other FBs as dictated by the design
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CoolRunner-II CPLD Family software. The AIM minimizes both propagation delay and power as it makes attachments to the various FBs.
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also available. Table 5 summarizes various supported voltage standards associated with specific part capacities. All inputs and disabled outputs are voltage tolerant up to 3.3V. The CoolRunner-II family supports SSTL2-1, SSTL3-1 and HSTL-1 high-speed I/O standards in the 128-macrocell and larger devices. Figure 4 details the I/O pin, where it is noted that the inputs requiring comparison to an external reference voltage are available. These I/O standards all require VREF pins for proper operation. The CoolRunner-II CPLD allows any I/O pin to act as a VREF pin, granting the board layout engineer extra freedom when laying out the pins.However, if VREF pin placement is not done properly, additional VREF pins may be required, resulting in a loss of potential I/O pins or board re-work. See XAPP399 for details regarding VREF pins and their placement. VREF has pin-range requirements that must be observed. The Xilinx software aids designers in remaining within the proper pin range.
I/O Block
I/O blocks are primarily transceivers. However, each I/O is either automatically compliant with standard voltage ranges or can be programmed to become so. See XAPP382 for detailed information on CoolRunner-II I/Os. In addition to voltage levels, each input can selectively arrive through Schmitt-trigger inputs. This adds a small time delay, but substantially reduces noise on that input pin. Approximately 500 mV of hysteresis will be added when Schmitt-trigger inputs are selected. All LVCMOS inputs can have hysteresis input. Hysteresis also allows easy generation of external clock circuits. The Schmitt-trigger path is best seen in Figure 4. See Table 5 for Schmitt-trigger compatibility with I/O standards. Outputs can be directly driven, 3-stated or open-drain configured. A choice of slow or fast slew rate output signal is
Available on 128 Macrocell Devices and Larger To AIM To Macrocell Direct Input Hysteresis VREF Global termination Pullup/Bus-Hold
Enabled CTE PTB 4 GTS[0:3] CGND Open Drain Disabled
VCCIO
From Macrocell
DS090_04_121201
Figure 4: CoolRunner-II CPLD I/O Block Diagram Table 5 summarizes the single ended I/O standard support and shows which standards require VREF values and board termination. VREF detail is given in specific data sheets. Table 5: CoolRunner-II CPLD I/O Standard Summary IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 HSTL_1 SSTL2_1 SSTL3_1 VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Input VREF N/A N/A N/A N/A N/A 0.75 1.25 1.5 Board Termination Voltage (VTT) N/A N/A N/A N/A N/A 0.75 1.25 1.5 Schmitt-trigger Support Optional Optional Optional Optional Not optional Not optional Not optional Not optional
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CoolRunner-II CPLD Family effectively blocking controlled switching signals so they do not drive internal chip capacitances. Output signals that do not switch, are held by the bus hold feature. Any set of input pins can be chosen to participate in the DataGATE function. Figure 5 shows the familiar CMOS ICC versus switching frequency graph. With DataGATE, designers can approach zero power, should they choose to, in their designs Figure 6 shows how DataGATE basically works. One I/O pin drives the DataGATE Assertion Rail. It can have any desired logic function on it. It can be as simple as mapping an input pin to the DataGATE function or as complex as a counter or state machine output driving the DataGATE I/O pin through a macrocell. When the DataGATE rail is asserted high, any pass transistor switch attached to it is blocked. Note that each pin has the ability to attach to the AIM through a DataGATE pass transistor, and thus be blocked. A latch automatically captures the state of the pin when it becomes blocked. The DataGATE Assertion Rail threads throughout all possible I/Os, so each can participate if chosen. Note that one macrocell is singled out to drive the rail, and that macrocell is exposed to the outside world through a pin, for inspection. If DataGATE is not needed, this pin is an ordinary I/O.
Output Banking
CPLDs are widely used as voltage interface translators. To that end, the output pins are grouped in large banks. The XC2C32 and XC2C64 devices are not banked, but the new XC2C32A and XC2C64A devices have two banks. The medium parts (128 and 256 macrocell) support two output banks. With two, the outputs will switch to one of two selected output voltage levels, unless both banks are set to the same voltage. The larger parts (384 and 512 macrocell) support four output banks split evenly. They can support groupings of one, two, three or four separate output voltage levels. This kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DataGATE
Low power is the hallmark of CMOS technology. Other CPLD families use a sense amplifier approach to creating product terms, which always has a residual current component being drawn. This residual current can be several hundred milliamps, making them unusable in portable systems. CoolRunner-II CPLDs use standard CMOS methods to create the CPLD architecture and deliver the corresponding low current consumption, without doing any special tricks. However, sometimes designers would like to reduce their system current even more by selectively disabling circuitry not being used. The patented DataGATE technology was developed to permit a straightforward approach to additional power reduction. Each I/O pin has a series switch that can block the arrival of free running signals that are not of interest. Signals that serve no use may increase power consumption, and can be disabled. Users are free to do their design, then choose sections to participate in the DataGATE function. DataGATE is a logic function that drives an assertion rail threaded through the medium and high-density CoolRunner-II CPLD parts. Designers can select inputs to be blocked under the control of the DataGATE function,
ICC
0
Frequency
DS090_05_101001
Figure 5: CMOS ICC vs. Switching Frequency Curve
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CoolRunner-II CPLD Family
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DataGATE Assertion Rail
MC1 MC2 MC1 MC2
Latch
To AIM
PLA
Latch
PLA
Latch
To AIM
MC16 MC1 MC2 MC16 MC1 MC2
To AIM
AIM
PLA
PLA
Latch
Latch
To AIM
MC16 MC16
To AIM
DS090_06_111201
Figure 6: DataGATE Architecture (output drivers not shown)
Global Signals
Global signals, clocks (GCK), sets/resets (GSR) and output enables (GTS), are designed to strongly resemble each other. This approach enables design software to make the best utilization of their capabilities. Each global capability is supplemented by a corresponding product term version. Figure 7 shows the common structure of the global signal trees. The pin input is buffered, then drives multiple internal global signal traces to deliver low skew and reduce loading delays. The DataGATE assertion rail is also a global signal.
Additional Clock Options: Division, DualEDGE, and CoolCLOCK
Division
Circuitry has been included in the CoolRunner-II CPLD architecture to divide one externally supplied global clock by standard values. Division by 2,4,6,8,10, 12, 14 and 16 are the options (see Figure 8). This capability is supplied on the GCK2 pin. The resulting clock produced will be 50% duty cycle for all possible divisions. Note that a Synchronous Reset (CDRST) is included to guarantee no runt clocks can get through to the global clock nets. Note that again, the signal is buffered and driven to multiple traces with minimal loading and skew.
DualEDGE
Each macrocell has the ability to double its input clock switching frequency. Figure 9 shows the macrocell flip-flop with the DualEDGE option (doubled clock) at each macrocell. The source to double can be a control term clock, a product term clock or one of the available global clocks. The ability to switch on both clock edges is vital for a number of synchronous memory interface applications as well as certain double data rate I/O applications.
DS090_07_101001
Figure 7: Global Clocks (GCK), Sets/Resets (GSR) and Output Enables (GTS)
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CoolRunner-II CPLD Family drain, the clock power can be reduced by driving the net at half frequency, then doubling the clock rate using DualEDGE triggering at the macrocells. Figure 10 shows how CoolCLOCK is created by internal clock cascading with the divider and DualEDGE flip-flop working together. See XAPP378 for more detail.
CoolCLOCK
In addition to the DualEDGE flip-flop, additional power savings can be had by combining the clock division circuitry with the DualEDGE circuitry. This capability is called CoolCLOCK and is designed to reduce clocking power within the CPLD. Because the clock net can be an appreciable power
GCK2
Clock In
/2 /4 /6 /8 /10 /12 /14 /16
CDRST CDRST
DS090_08_121201
Figure 8: Clock Division Circuitry for GCK2
D/T
Q
PTC GCK0 GCK1 GCK2
FIF CE Latch CK DualEDGE
CLK_CT PTC
DS090_09_121201
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
D/T
Q
PTC GCK0 GCK1 GCK2
FIF CE Latch CK DualEDGE
CTC PTC
GCK2
Clock In
/2 /4 /6 /8 /10 /12 /14 /16
Synch Rst Synch Reset
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Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
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Design Security
Designs can be secured during programming to prevent either accidental overwriting or pattern theft via readback. Four independent levels of security are provided on-chip, eliminating any electrical or visual detection of configuration patterns. These security bits can be reset only by erasing the entire device. See WP170 for more detail.
Timing Model
Figure 11 shows the CoolRunner-II CPLD timing model. It represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal will incur if the signal passes through such a resource. Timing reports are created by tallying the incremental signal delays as signals progress within the CPLD. Software creates the timing reports after a design has been mapped onto the specific part, and knows the specific delay values for a given speed grade. Equations for the higher level timing values (i.e., TPD and FSYSTEM) are available. Table 6 summarizes the individual parameters and provides a brief definition of their associated functions. Xilinx application note XAPP375 details the CoolRunner-II CPLD family timing with several examples.
TF TLOGI2 TIN THYS TDIN THYS TGCK S/R THYS TGSR THYS TGTS THYS
XAPP375_03_010303
TPDI D/T
TCOI TSUI THI TECSU TECHO
TLOGI1
TSLEW TOUT
TCT
CE
TAOI
TEN TOEM
Figure 11: CoolRunner-II CPLD Timing Model Table 6: Timing Parameter Definitions Symbol
Buffer Delays
Table 6: Timing Parameter Definitions (Continued) Symbol
Macrocell Delays
Parameter Input Buffer Delay Direct data register input delay Global clock (GCK) buffer delay Global set/reset (GSR) buffer delay Global output enable (GTS) buffer delay Output buffer delay Output buffer enable/disable delay Output buffer slew rate control delay Control Term delay (single PT or FB-CT) Single P-term logic delay Multiple P-term logic delay adder
Parameter Macro cell input to output valid Macro register setup before clock Macro register hold after clock Macro register enable clock setup time Macro register enable clock hold time Macro register clock to output valid Macro register set/reset to output valid Hysteresis selection delay adder Feedback delay Macrocell to Global OE delay
TlN TDIN TGCK TGSR TGTS TOUT TEN TSLEW TCT TLOGI1 TLOGI2
TPDI TSUI THI TECSU TECHO TCOI TAOI THYS TF TOEM
P-term Delays
Feedback Delays
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CoolRunner-II CPLD Family as well. The internal controllers can operate as fast as 66 MHz. Table 7: JTAG Instructions Code 00000000 00000011 11111111 Instruction EXTEST PRELOAD BYPASS INTEST IDCODE HIGHZ CLAMP Description Force boundary scan data onto outputs Latch macrocell data into boundary scan cells Insert bypass register between TDI and TDO Force boundary scan data onto inputs and feedbacks Read IDCODE Force output into high impedance state Latch present output state
Programming
The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment. See CoolRunner-II Application Notes for more information on how to program.
In System Programming
All CoolRunner-II CPLD parts are 1.8V in system programmable. This means they derive their programming voltage and currents from the 1.8V VCC (internal supply voltage) pins on the part. The VCCIO pins do not participate in this operation, as they may assume another voltage ranging as high as 3.3V down to 1.5V. A 1.8V VCC is required to properly operate the internal state machines and charge pumps that reside within the CPLD to do the nonvolatile programming operations. The JTAG interface buffers are powered by a dedicated power pin, VCCAUX, which is independent of all other supply pins. VCCAUX must be connected. Xilinx software is provided to deliver the bit-stream to the CPLD and drive the appropriate IEEE 1532 protocol. To that end, there is a set of IEEE 1532 commands that are supported in the CoolRunner-II CPLD parts. Programming times are less than one second for 32 to 256 macrocell parts. Programming times are less than four seconds for 384 and 512 macrocell parts. Programming of CoolRunner-II CPLDs is only guaranteed when operating in the commercial temperature and voltage ranges as defined in the device-specific data sheets. 00000010 00000001
11111101 USERCODE Read USERCODE 11111100 11111010
Power-Up Characteristics
CoolRunner-II CPLD parts must operate under the demands of both the high-speed and the portable market places, therefore, they must support hot plugging for the high-speed world and tolerate most any power sequence to its various voltage pins. They must also not draw excessive current during power-up initialization. To those ends, the general behavior is summarized as follows: 1. I/O pins are disabled until the end of power-up. 2. As supply rises, configuration bits transfer from nonvolatile memory to SRAM cells. 3. As power up completes, the outputs become as configured (input, output, or I/O). 4. For specific configuration times and power up requirements, see the device specific data sheet. CoolRunner-II CPLD I/O pins are well behaved under all operating conditions. During power-up, CoolRunner-II devices employ internal circuitry which keeps the devices in the quiescent state until the VCCINT supply voltage is at a safe level (approximately 1.3V). In the quiescent state, JTAG pins are disabled, and all device outputs are disabled with the pins weakly pulled high, as shown in Table 8. When the supply voltage reaches a safe level, all user registers become initialized, and the device is immediately available for operation, as shown in Figure 12. Best results are obtained with a smooth VCC rise in less than 4 ms. Final VCC value should occur within 1 second. If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with a weak pull-up. The JTAG pins are enabled to allow the
On-The-Fly Reconfiguration (OTF)
Xilinx ISE 5.2i supports OTF for CoolRunner-II CPLDs. This permits programming a new nonvolatile pattern into the part while another pattern is currently in use. OTF has the same voltage and temperature specifications as system programming. During pattern transition I/O pins are in high impedance with weak pullup to VCCIO. Transition time typically lasts between 50 and 300 s, depending on density. See XAPP388 for more information.
JTAG Instructions
Table 7 shows the commands available to users. These same commands may be used by third party ATE products,
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CoolRunner-II CPLD Family device to be programmed at any time. All devices are shipped in the erased state from the factory. Applying power to a blank part may result in a higher current flow as the part initializes. This behavior is normal and may persist for approximately 2 seconds, depending on the power supply ramp. If the device is programmed, the device inputs and outputs take on their configured states for normal operation. The JTAG pins are enabled to allow device erasure or boundary-scan tests at any time.
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VCCINT
1.3V 3.8 V (Typ) (Typ)
0V No Power Quiescent State User Operation Quiescent State No Power
Initialization Transition of User Array
x382_10
Figure 12: Device Behavior During Power Up
Table 8: I/O Power-Up Characteristics Device Circuitry
IOB Bus-Hold/Weak Pullup Device Outputs Device Inputs and Clocks Function Block JTAG Controller
Quiescent State Weak Pull-up Disabled Disabled Disabled Disabled
Erased Device Operation Weak Pull-up Disabled Disabled Disabled Enabled
Valid User Operation Bus-Hold/Weak Pullup As Configured As Configured As Configured Enabled
I/O Banking
CoolRunner-II CPLD XC2C32 and XC2C64 macrocell parts support a single VCCIO rail that can range from 3.3V down to 1.5V operation. Two VCCIO rails are supported on the XC2C32A, XC2C64A, 128 and 256 macrocell parts where outputs on each rail can independently range from 3.3V down to 1.5V operation. Four VCCIO rails are supported on the 384 and 512 macrocell parts. Any of the VCCIO rails can assume any one of the VCCIO values of 1.5V, 1.8V, 2.5V, or 3.3V. Designers should assign input and output voltages to a bank with VCCIO set at the voltage range of that input or output voltage. The VCC (internal supply voltage) for a CoolRunner-II CPLD must be maintained within 1.8V 5% for correct speed operation and proper in system programming.
applied to the VCCIO and VCC pins can occur in any order and the CoolRunner-II CPLD will not be damaged. For best results, we recommend that VCCIO be applied before VCCINT. CoolRunner-II CPLDs can reside on boards where the board is inserted into a "live" connector (hot plugged) and the parts will be well-behaved as if powering up in a standard way.
Development System Support
Xilinx CoolRunner-II CPLDs are supported by all configurations of Xilinx standard release development software as well as the freely available ISE WebPACK software available from www.xilinx.com. Third party development tools include synthesis tools from Cadence, Exemplar, Mentor Graphics, Synplicity, and Synopsys.
Mixed Voltage, Power Sequencing, and Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts support mixed voltage I/O signals. It is important to assign signals to an I/O bank with the appropriate I/O voltage. Driving a high voltage into a low voltage bank can result in negative current flow through the power supply pins. The power
ATE Support
Third party ATE development support is available for both programming and board/chip level testing. Vendors providing this support include Agilent, GenRad, and Teradyne. Other third party providers are expected to deliver solutions in the future.
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DS090 (v2.5) June 28, 2005 Product Specification
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CoolRunner-II CPLD Family
Absolute Maximum Ratings(1)
Symbol VCC(2) VI(3) TJ(4) TSTR Parameter Supply voltage relative to GND Input voltage relative to GND Maximum junction temperature Storage temperature Min. -0.5 -0.5 -40 -65 Max. 2.0 4.0 150 150 Unit V V C C
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. The chip supply voltage should rise monotonically. 3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to 4.5 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. The I/O voltage may never exceed 4.0V. 4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427.
Quality and Reliability Parameters
Symbol TDR NPE VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge(1) Parameter Min 20 1,000 2,000 Max Units Years Cycles Volts
Notes: 1. ESD is measured to 2000V using the human body model. Pins exposed to this limit can incur additional leakage current to a maximum of 10 A when driven to 3.9V.
Further Reading
Application Notes
http://direct.xilinx.com/bvdocs/appnotes/xapp375.pdf (Timing Model) http://direct.xilinx.com/bvdocs/appnotes/xapp376.pdf (Logic Engine) http://direct.xilinx.com/bvdocs/appnotes/xapp377.pdf (Low Power Design) http://direct.xilinx.com/bvdocs/appnotes/xapp378.pdf (Advanced Features) http://direct.xilinx.com/bvdocs/appnotes/xapp379.pdf (High Speed Design) http://direct.xilinx.com/bvdocs/appnotes/xapp380.pdf (Cross Point Switch) http://direct.xilinx.com/bvdocs/appnotes/xapp381.pdf (Demo Board) http://direct.xilinx.com/bvdocs/appnotes/xapp382.pdf (I/O Characteristics) http://direct.xilinx.com/bvdocs/appnotes/xapp383.pdf (Single Error Correction Double Error Detection)
http://direct.xilinx.com/bvdocs/appnotes/xapp384.pdf (DDR SDRAM Interface) http://direct.xilinx.com/bvdocs/appnotes/xapp387.pdf (PicoBlaze Microcontroller) http://direct.xilinx.com/bvdocs/appnotes/xapp388.pdf (On the Fly Reconfiguration) http://direct.xilinx.com/bvdocs/appnotes/xapp389.pdf (Powering CoolRunner-II) http://direct.xilinx.com/bvdocs/appnotes/xapp393.pdf (8051 Microcontroller Interface) http://direct.xilinx.com/bvdocs/appnotes/xapp394.pdf (Interfacing with Mobile SDRAM) http://direct.xilinx.com/bvdocs/appnotes/xapp399.pdf (Assigning CoolRunner-II VREF Pins)
CoolRunner-II Data Sheets
http://direct.xilinx.com/bvdocs/publications/ds090.pdf (CoolRunner-II Family Datasheet) http://direct.xilinx.com/bvdocs/publications/ds091.pdf (XC2C32 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds092.pdf (XC2C64 Datasheet)
DS090 (v2.5) June 28, 2005 Product Specification
www.xilinx.com
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CoolRunner-II CPLD Family http://direct.xilinx.com/bvdocs/publications/ds093.pdf (XC2C128 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds094.pdf (XC2C256 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds095.pdf (XC2C384 Datasheet) http://direct.xilinx.com/bvdocs/publications/ds096.pdf (XC2C512 Datasheet)
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CoolRunner-II White Papers
http://direct.xilinx.com/bvdocs/whitepapers/wp170.pdf (Security)
Packages
Package Drawings
Online Store
Xilinx Online Store
Revision History
The following table shows the revision history for this document. Date 01/03/02 07/04/02 07/24/02 09/24/02 01/28/03 02/26/03 03/12/03 10/09/03 01/26/04 02/26/04 05/21/04 07/30/04 01/10/05 03/07/05 04/15/05 06/28/05 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 Initial Xilinx release Revisions and updates Revisions and updates Additions to "Power Characteristics" section Addition of the "Further Reading" section Multiple minor revisions Minor revision to "Quality and Reliability Parameters" Update Hewlett-Packard to Agilent, OFR to OTF, and other revisions Incorporate links to Data Sheets, Application Notes, and Device Packages Change to Power-Up Characteristics, page 11. Change TFIN to TDIN. Add Schmitt-trigger I/O compatibility information. Added TSOL specification. Add XC2C32A and XC2C64A devices. Pb-free documentation. Changes to TSU and Fsystem to match individual data sheets. Added information about programming options, page 11. Changes to Table 1, TPD, TSU, TCO, and FSYSTEM1. Removed link to obsolete White Paper. Modifications to Table 5, IOSTANDARDs. Added Table 2, DC Characteristics. Change to FSYSTEM1 for XC2C128. Move to Product Specification Revision
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DS090 (v2.5) June 28, 2005 Product Specification

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